Image acquisition system

ABSTRACT

An image acquisition system for machine vision systems decouples image acquisition from the transmission of the image to a host processor by using a programmable imager controller to selectively disable and enable the transmission of data to the host and by using a system of buffers to temporarily store image data pending allocation of memory. This enables the image acquisition system to acquire images asynchronously and to change the exposure parameters on a frame-by-frame basis without the latency associated with the allocation of memory for storage of the acquired image. The system architecture of the invention further permits interruption and resumption of image acquisition with minimal likelihood of missing data. Data throughput is further enhanced by transmitting to the host only that data corresponding to the region of interest within the image and discarding the data from outside of the region of interest at the camera stage.

RELATED APPLICATIONS

[0001] The current application is a continuation-in-part of andincorporates by reference the commonly-owned, co-pending U.S.Provisional Application No. 60/038,690, filed on Feb. 7, 1997 and thecommonly-owned and copending U.S. Provisional Application 60/020,885,filed on Jun. 28, 1996.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to image acquisition systems, andmore particularly to image acquisition systems suitable for machinevision systems that capture and process optical images.

[0003] Conventional image acquisition systems have been used for decadesto acquire and process optical images. The conventional systemstypically employ one or more video cameras that acquire an image andframe grabber boards that store and/or process the image. These systemsare relatively easy to connect since the components of the system arewell characterized, readily understood, and result in predictableperformance.

[0004] Today's modem manufacturing and industrial installations arebecoming increasingly automated to increase quality and reduce costs tobetter compete in the global market. Consequently, these installationstypically employ machine vision systems which are used to monitorproduction processes, position selected components, and to perform otherimportant manufacturing tasks. There is, however, a mismatch between therequirements of modern machine vision systems and the design goals ofexisting imaging technology typically used with machine vision systems.

[0005] Conventional image acquisition systems are designed to provideeither a continuous flow of images or a predictable flow of images at afixed rate determined by human awareness and response times, and at thelowest possible cost. With a new frame being transmitted every {fraction(1/60)} second, missing lines and/or frames in such a system aretolerable because they are generally unnoticed by a human viewer. Thefixed rate of image capture and delivery in conventional imageacquisition systems is just fast enough to seem infinitely fast orseamless to human perception. Because errors that occur during imageacquisition and transfer, such as dropped lines and frames, are onlypresented to a viewer for {fraction (1/60)}th of a second, and becausethe human eye acts as a time integrator, these intermittent errors arerarely perceptible to a human observer.

[0006] On the other hand, machine vision systems often make decisionsbased on a single still image. Because of this, machine vision systemsrequire considerably higher resolution, contrast, and tolerance for dataintegrity than conventional image acquisition systems. For example, ifthe machine vision system is looking for normal process variations inmanufactured parts, any imaging errors can result in the inappropriaterejection of a part. This leads to unnecessary part waste and anincrease in the total costs of production.

[0007] Errors in an image acquisition system include imaging errors andprocessing errors. Processing errors, such as dropped lines and frames,arise from errors that occur as image data travels from the camera tothe host computing system. Imaging errors arise in the camera itself orin the environment outside the camera. The former we refer to as sensorerrors and the latter we refer to as scene errors.

[0008] Sensor errors typically arise from differences betweenphotosensitive elements, (e.g., photosites in a charge-coupled device)that form part of the image acquisition system. As a result of thesedifferences, a pair of photosensitive elements may respond differentlyto the same level of illumination. These differences arise from normalprocess variations in the manufacture of the photosensitive elements orfrom temperature differences between otherwise identical photosensitiveelements.

[0009] Scene errors are those errors that arise from incorrectlyilluminating a scene. Since ambient lighting conditions cannot becontrolled to the same level of precision as that resolvable by a modemmachine vision system, subtle variations in lighting levels or colors,due, for example, to aging of light sources, can degrade the performanceof the machine vision system.

[0010] Unlike conventional image acquisition systems which obtain imageseither continuously or at regular intervals, machine vision systems canrequire images at unpredictable times. For example, in an automatedinspection line, the objects to be inspected may not be spaced apartregularly enough on the conveyor belt to permit periodic imageacquisition. Consequently, a machine vision system does not have theluxury of knowing, in advance, when an image is to be received.

[0011] A machine vision system should also be ready to acquire an imagealmost immediately upon request. For example, in the automatedinspection line described above, if an object to be inspected is aboutto enter the camera's field of view, it is preferable that an image beacquired rapidly, before the object leaves the camera's field of view.

[0012] Because machine vision systems often have to obtain multipleimages in rapid succession, a need exists to rapidly transmit image datato a processor of a host system. Prior art machine vision systemsgenerally interrupt the host processor to obtain a starting memoryaddress in which to place an image or portion thereof before the actualimage acquisition and transfer can begin. In such systems, referred toas “software scatter/gather” systems, the host processor plays asignificant role in image acquisition and transfer. This reliance on ascarce resource such as the host processor results in latency periodsduring which image acquisition and transfer cannot occur because thehost processor is busy performing other tasks. These latency periods ofuncertain duration make it difficult, if not impossible, for a machinevision system to repeatedly acquire an image on demand. When the latencyperiod becomes excessively long, collisions can occur in the data pathas data from subsequent images arrives faster than data from previousimages can be processed. This results in lost or erroneous data.

[0013] In other machine vision systems, referred to as “hardwarescatter/gather” systems, data transfer is performed by a direct memoryaddress technique (DMA). Although these systems do not require theassistance of the host processor to access memory, they typicallyrequire that a memory segment be dedicated to their use. Thedisadvantage of this method is that the dedicated memory becomesunavailable for use by other processing tasks, even when it is not beingused for image transfer.

[0014] In systems of this type, data collisions, as described above, canbe ameliorated by dividing the dedicated memory into two blocks. Thisenables the system to place an incoming image into the first memoryblock while processing the image in the second memory block. Once thesystem finishes processing the system in the second block, it can beginprocessing the image in the first block, thereby freeing the secondblock to receive another incoming image. A disadvantage of this systemtype is that, when used in conjunction with a multithreaded computingenvironment, the complexity of programming this task becomes rapidlyunmanageable.

[0015] It is also desirable for modem machine vision systems toautonomously determine whether or not an image should be acquired. Forexample, in an inspection line, the objects to be inspected may not bespaced at regular intervals. This raises the problem of how to acquirean image only when an object to be inspected is in the camera's field ofview or in a particular region within the camera's field of view.

[0016] Prior art systems attempt to solve this problem by triggering thecamera with an external sensor located outside of the machine visionsystem. These sensors, however, are typically difficult to interfacereliably with the machine vision system. Moreover, latency associatedwith the machine vision system can make it difficult to reliablyposition the object to be inspected in the correct region of thecamera's field of view.

[0017] Further important constraints imposed by conventional imageacquisition systems include the relatively fixed field of view,relatively fixed frequency of image capture, fixed and relatively lowrate of image transfer to host computer memory (or relatively expensivetransfer of image), and lack of data integrity, arising, for example,from gray scale errors due to several causes including pixel jitter andskew, or from lost data such as dropped lines and frames.

[0018] Additionally, current machine vision systems are relativelyexpensive to install and operate. Another drawback of these systems isthat they are unable to change the form of the acquired image data inreal time, in other words, between each acquired frame or shot.

[0019] Modem machine vision systems have been developed to address someof these drawbacks. One example devised to ameliorate some of thesedrawbacks includes the use of expensive custom application-specificcircuitry to provide high fidelity and low error image acquisition.These custom systems are typically very expensive to acquire and verydifficult to integrate with existing machine vision systems.

[0020] There thus exists a need in the art for an image acquisitionsystem suitable for use with modem machine vision systems that isflexible and provides for high fidelity asynchronous image acquisitionand transfer.

SUMMARY OF THE INVENTION

[0021] The image acquisition system of the present invention eliminatesthese and other sources of image acquisition errors by integrating mostof the image acquisition components into one dedicated machinearchitecture. This dedicated architecture can be utilized to performpreliminary image processing operations in real-time such as correctingeach acquired image for both hardware errors and scene errors,recalibrating the sensor array in real time to correct for errors due todifferences between pixels or errors in scene illumination, or otherwisespatially filtering the image in real-time, all without burdening thehost processor.

[0022] A system according to the invention includes an image acquisitionstage for acquiring at least a region of interest from an image inresponse to a trigger signal. The trigger signal can incorporateexposure information for the image acquisition stage and instructionsfor specifying the region of interest. This information can be changedon a frame-by-frame basis, in real time and on the fly.

[0023] The system then transfers either all or part of the datarepresenting the image to the host processor by way of a sequence oftemporary buffers. These buffers enable the system to decouple theprocess of image acquisition from image transfer, thereby enabling thesystem to acquire images without having to wait for the host processorto allocate memory for storage of the system. The sequence of temporarybuffers also enables a system according to the invention to interruptthe process of transmission either between images or in the middle ofthe image and to resume transmission with little likelihood of dataloss.

[0024] The data throughput for a system according to the invention iscontrolled by means of a programmable imager controller which can drivethe transfer of data from a CCD array or other solid state imagingdevice to the host processor at variable rates in response to the stateof the buffers and in response to instructions from the host processor.This programmable imager controller further increases system throughputby transmitting to the host processor only data from within the regionof interest and discarding data from outside the region of interest.Since data can be discarded more quickly that it can be transmitted,this increase in throughput can be substantial when the region ofinterest is much smaller than the overall image.

[0025] The system of the invention can also control selected systemparameters during the acquisition of one or more images. Theseparameters include the time and duration of exposure, the particularregion of interest within the field of view, the particular mode ofoperation of the system, and other parameters that define the frameworkfor image acquisition and which would be obvious in light of thisdisclosure to one of ordinary skill in optical and electricalengineering. A significant advantage of the present invention is thatthese parameters can be changed in real time, between shots or frames,without sacrificing bandwidth. This feature allows the system todynamically respond to requests during the image acquisition process.

[0026] The system also enables images to be acquired asynchronously andvirtually on demand without the need to wait for the availability ofsystem memory to store the image. The system achieves this by separatingthe acquisition of an image by the camera, a task of short andrelatively predictable duration, from the task of transmitting the imagefrom the camera to the host processor, a task having an unpredictableand potentially long duration. Consequently, the image capturing stagecan be performed independently of the image transfer stage. Whennecessary, the acquired image can be stored temporarily in memory, suchas in a data FIFO register, while the system waits for a memory addressto place the image into. Because of this separation between imageacquisition and image transfer, the system of the invention can acquirean image without the need to await a memory address in which to placethe image. The system is thus not hampered by the latency associatedwith conventional image acquisition systems. Additionally, the systemcan thus process requests for an image without requiring the destinationaddress in advance.

[0027] When the data FIFO register approaches its capacity, it canassert an interrupt to halt image acquisition as described below. Thisis achieved by interposing a feedback loop between a camera and theimage acquisition board. This feedback loop enables the acquisitionboard to temporarily and immediately halt image acquisition and transferwhenever there is too much data traffic to permit the reliabletransmission of data. According to one practice of the invention, dataalready acquired by the camera is temporarily stored in the camerathroughout the duration of the interruption. By incorporating thisfunction into the dedicated architecture, the present invention relievesthe host processor from burdensome data management tasks. This providesfor an increase in image fidelity (data integrity) with a correspondingdecrease in the occurrence of errors when acquiring images as well as anincrease in overall image throughput.

[0028] An additional feature of the present invention is thatinterruption of image acquisition and transfer, as described above, canoccur either at the end of a frame, at the end of a line within animage, or at the end of any preselected section of an image. Theflexibility achieved by permitting the transfer of image data in unitssmaller than the entire image enables the system to take advantage ofsmall gaps in data traffic that it would otherwise be unable to use, aswell as enables the system to rapidly acquire and transfer image data.

[0029] Another feature of the invention is that the system acquires datasignificantly faster than prior art systems, including hybridconventional systems employing conventional imaging and machine visionsystems. According to one practice of the invention, images can beacquired and transferred to the system's image signal processor up to 30times faster than conventional systems, while providing for flexible,high speed control and transfer of the image data.

[0030] Unlike prior art systems in which a portion of memory isdedicated to hold the image to be processed, the system of the presentinvention exploits modern operating systems' ability to perform dynamicmemory allocation. This permits the system to allocate only as muchmemory as is necessary to process an image and to allocate that memoryonly when it is necessary to do so and on an image-by-image basis. Oncethe image processing task has been completed, memory allocated to thattask can be released for use in other processing tasks.

[0031] According to one aspect, the system acquires imagesasynchronously and independently of the host processor.

[0032] This is facilitated by the separation of image acquisition andtransfer, thereby permitting acquisition to occur before memory to storethe image is made available. The system is also configured to place atime-stamp on the acquired image. According to one practice, controllerhardware of the host device monitors the system for a camera triggersignal, which triggers the camera. This avoids the latency associatedwith having the host processor monitor and time stamp the image.

[0033] The present invention also provides a structure for autonomouslydeciding, based on an image in the camera's field of view, whether ornot to acquire an image. The system of the invention accomplishes thisby designating a trigger region within the camera's field of view andprocessing the image from the trigger region to determine if the imagein a region of interest within the camera's view should be acquired. Thesystem processes the portion of the image within the designated triggerregion independently of the host processor and at relatively high samplerates.

[0034] The foregoing control of the image acquisition process is thuscontrolled on an image-by-image basis in a dedicated architecture thatis smaller and significantly less costly than systems heretofore known,thus dramatically reducing the overall cost of the image acquisitionsystem. Additional features of the invention which aid in the reductionof cost include the simplification of the data paths.

[0035] The image acquisition system of the present invention includes animage acquisition element, such as a camera, for acquiring an image anda programmable control element which selectively and programmablyinitiates the performance of a number of selected functions by the imageacquisition element. These functions can include the initiation andtermination of image acquisition, the selection of a particular regionof interest within the acquired image, calibration or filtering of theoutputs of the photosensitive elements that form part of the imageacquisition system, definition of a trigger region, or the purging ofcharge from the photosensitive elements. The image acquisition by thecamera can also be interrupted, in real-time, such that at least aportion of the image is temporarily stored in the camera. Thisinterruption sequence allows the image acquisition system of theinvention to process any previously transferred image data in highlyreliable manner.

[0036] The system can be mounted on an acquisition board that functionsas an interface between the camera and a conventional host computingsystem. The acquisition board manages the transfer of image data betweenthe camera and the host computing system, where the image data isultimately processed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The foregoing and other objects, features and advantages of theinvention will be apparent from the following description and theaccompanying drawings in which like reference characters refer to thesame parts throughout the different views.

[0038]FIG. 1 is a schematic block diagram of the image acquisitionsystem of the present invention.

[0039]FIG. 2 is a more detailed schematic block diagram of the imageacquisition system of FIG. 1.

[0040]FIG. 3A-3B are schematic depiction's of the vertical andhorizontal register arrays of the camera component of the acquisitionsystem of FIG. 1.

[0041]FIG. 4 is a more detailed schematic depiction of the imageacquisition device of FIG. 1.

[0042]FIG. 5 is a more detailed schematic depiction of the camera ofFIG. 2.

[0043]FIG. 6 is tabular depiction of the states of selected gates of theprogrammable imager controller of FIG. 5 during selected modes ofoperation.

[0044]FIG. 7 is a flow chart state diagram illustrating the operationsequence of the programmable imager controller according to one mode ofoperation.

[0045]FIG. 8A is block diagram of the pixel sensitivity correction unitused to calibrate or filter the output of the photosensitive elementsthat constitute the image acquisition elements.

[0046]FIG. 8B is a block diagram of a pixel sensitivity correction unitconnected to the digital input of the AID converter component of theacquisition system of FIG. 1.

[0047]FIG. 9 is an illustration of the trigger region and a region ofinterest within the camera's field of view.

DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0048]FIG. 1 is a schematic illustration of the image acquisition system10 according to the teachings of the present invention. The illustratedsystem 10 includes a central or host computing system 12. The hostcomputing system can be any conventional computing apparatus and cancomprise a display monitor and a dedicated signal processor or can be aclient signal processor which forms part of a larger area network, suchas a LAN or WAN. The host computing system 12 is preferably incommunication with an acquisition board 14, which in turn is coupled toone or more external image capturing devices 16, e.g., cameras. Theacquisition board 14, although illustrated as being located outside ofthe host system 12, can form part of that system as will be appreciatedby those of ordinary skill. Consequently, occasionally the combinationof the two will be referred to as the host system. According to apreferred practice, the acquisition board is similar to a PCI bus cardwhich interfaces with the PCI bus of the host system 12, according tothe teachings of the present invention.

[0049] Those of ordinary skill will recognize that a single acquisitionboard 14 can be used to operate a number of cameras 16. Conversely, aseparate acquisition board 14 can also be used for each camera 16 of theacquisition.

[0050] The illustrated cameras 16 each include a programmable imagercontroller stage 20 which is coupled to an image capturing element 24.The acquisition board 14 preferably generates control signals which aretransferred to the programmable imager controller 20 along communicationpath 28. The output of the camera element 16 is transferred to theacquisition board along data output path 30 for storage and/orprocessing by the host system 12.

[0051]FIG. 2 is a more detailed schematic depiction of the imagecapturing element 16, acquisition board 14 and host computing system 12of the present invention. The illustrated host computing system 12preferably includes a bus 100, a display controller 106, a memory bus110, a memory module 116 representing actual physical memory, a hostprocessor 120, a co-processor 124, and a virtual memory block 128 thatillustratively stores selected executable and dynamic link libraries andcode, designated as code modules 132-138, as well as selected memory forthe image data regions, designated as destination addresses 142-146.Those of ordinary skill in computer and electrical engineering willreadily understand the operational relationship between the memory, bothphysical and virtual, and the software resident on the host computingsystem 12.

[0052] The bus 100 preferably interfaces and communicates with theacquisition board 14 and provides structure that allows for the flow ofimage data between the camera 16 and the host computing system 12. Theterm “bus” is intended to include any suitable data signal transmissionpath, and is preferably a high bandwidth data transmission channel, suchas a PCI bus. The display controller 106 preferably communicates withboth the bus 100 and the memory bus 110 to allow the controller 106 todisplay the acquired image data on the display monitor 12A, such as aVGA monitor, and to access stored instructions. The illustratedco-processor 124 is preferably coupled to both the bus 100 and thememory bus 110 and serves to direct the acquired image data. The use ofthis IO controller, i.e. “bridge chips” reduces the need to interruptthe host processor 120 to process the image data, and thus decreases theoverall processing time and increases the processing rate of the imageacquisition system 10.

[0053] The image acquisition system 10 can operate, according to onepractice, in response to externally applied triggers or in response tosignals generated internally by selected software code stored in thememory 128 of the central system 12. Specifically, selected imagingmodes of operation can be rapidly chosen by initiating a request to thesystem 10. The term “rapidly” is intended to mean initiating the requestin less than or equal to about 32 ms, and, preferably in less than orequal to about 1 ms. For example, a request can be made by the camerainterface executable program, referred to as cam.exe 132, or by selectedclient software (for example an image analysis or machine visionapplication program), referred to herein as client.exe 134. Theexecutable file 134 thus uses the image acquisition system 10 as asource of image data.

[0054] The terminology used herein is appropriate for systems installedin computers employing Microsoft's Windows 3.11 and DOS v. 6.x operatingsystems. When used with other operating systems, for example Windows NTor VME systems, similar terminology will apply. The structure of thesoftware code designated by cam.exe, client.exe, and the dynamic linklibraries can be easily constructed by the ordinarily skilled computerand electrical engineer by reference to the description of the operationof the image acquisition system 10 of this specification.

[0055] According to one practice, when the host computer loads or bootsthe executable program cam.exe 132, a selected environment isestablished in the host computer that the camera system employs toservice requests from either a user, through the computer's keyboard andmouse, or from an autonomous executable code block, such as the machinevision program client.exe 134. At a minimum, the program incorporatingan interrupt code (interrupt service routine) is loaded into the memory128 of the host computing system 12. The role of the interrupt code isto rapidly notify either cam.exe 132 or client. exe 134 that an imagebuffer has been filled with the data it requested and is ready forviewing and/or processing by the requester. If the program cam.exe 132needs to respond directly to user requests, it calls selected dynamiclink libraries (DLL's). These DLLs, such as cam.dll, are typically usedto store instantaneously accessible lists of functions and resources orto allocate virtual and physical memory for image buffers located in thehost computing system 12. Alternatively, when the program client.exe 134issues requests for an image directly, it allocates sufficient bufferspace in memory by making direct calls to cam.dll 138.

Camera Setup

[0056] In all modes of operation, either cam.exe 132 or client.exe 134establishes the operating framework for the image acquisition system 10by providing selected camera setup information, including the particularmode of camera operation, the particular region of interest, and properexposure times, and by providing host memory setup requirements,including image buffers to receive, hold and process the image data forone or more cameras 16. These programs can thus be used to generate thecamera instructions stored in the camera setup store 48 and reservedphysical addresses for image data in the destination address store 90,as discussed further below.

[0057] As used herein the term “region of interest” is intended toinclude a region or portion of an acquired image that is smaller in oneor more spatial or axial dimensions than the entire image acquired bythe image acquiring device or system. The region of interest ispreferably selectable. Additionally, those of ordinary skill willrecognize that the programs can establish multiple and different regionsof interest which are loaded into the camera setup store 48 and thedestination address store 90, as described in further detail below.These multiple regions of interest allow the system to dynamicallyacquire an image and process different selected portions of the entireacquired image. Additionally, these multiple regions of interest allowthe system to trigger acquisition of an image from one region ofinterest based on the content found in another region of interest.

[0058] According to one preferred practice, the region of interest canbe specified by providing the line and pixel number of the upper leftcorner of a rectangular region in the image and similar information forthe lower right hand corner of the region. The filled image buffersestablished by the host operating system can be areas of contiguousvirtual memory that are reserved and mapped to physical regiments inselected and variable block sizes, e.g., 512 byte to 4K byte blocks, andthat have a defined initial physical memory address, denoted as memorylocations 142-146. Those of ordinary skill will appreciate that imagebuffers contiguous in virtual memory space may be realized bynon-contiguous locations in physical memory space. It is anticipated bythe teachings of the present invention that only within each physicalblock are physical addresses contiguous. This facilitates theasynchronous mixing of data into one DMA channel from multiple sourcesduring multiple camera acquisitions.

[0059] All of the foregoing information is communicated to the camera16, to the acquisition board 14 and to the host computing system 12 inthe form of a call, in a language specified for and compatible with theimage acquisition system, to a selected code module, for example,cam.dll 138. The selected code module responds by making API or similarcalls to the operating system of the host computing system 12 toallocate one or more regions of contiguous virtual memory, typically insizes ranging between 1-300K byte and larger. Each such region ofcontiguous virtual memory is divided into subsets, typically 1-4K byteblocks, that can be a size convenient for the operating system. Theoperating system is then queried for the physical address of the firstbyte in each of these subsets. The foregoing physical addresses arecommunicated, via API (application programming interface) or similarcalls, to the camera destination address store 90. In a DOS/Windows/PCIenvironment, each subset is itself contiguous in physical memory. Theprogram cam.dll 138 transfers this information into on-board memory,which directly controls the cameras and which can reside in, among otherlocations, an input-output bus 102 (typically a PCI bus). The beginningaddresses of the image buffer physical memory block for each imagebuffer are then stored in a selected memory location, designated as thecamera destination address store 90. Meanwhile, the exposure times,camera modes, and regions of interest are also loaded into the camerasetup store 48.

[0060] Image data is transferred to the foregoing memory allocated forimage buffers via direct memory address (DMA) transfers that typicallydo not require processing by the host processor 120. Hence, the hostprocessor 120 need only be interrupted upon completion of an imagetransfer. Those of ordinary skill in computer and electrical engineeringwill appreciate the type of code that can be employed to perform theforegoing and following actions.

[0061] At the same time that it is transferred to host physical memory,image data can also be directed, via DMA transfer, to a displaycontroller 106. A look up table (LUT) 96 converts pixel data in realtime into a form appropriate for the host computing system 12 and itsdisplay controller 106.

Initiating Image Acquisition

[0062] With further reference to FIG. 2, the acquisition board 14includes an external trigger interface 34 having a plurality of externaltrigger inputs 36 to accept signals generated by a variety of externalsources, including the host system 12. Upon receiving an appropriatesignal through the trigger input 36, the external trigger interface 34generates trigger output signal 38 instructing the camera loader 42which camera or array of cameras to use.

[0063] The illustrated camera loader 42 has multiple inputs, e.g.,supports n inputs, and generates one or more camera trigger signals 44that drive one or more cameras 16 designated by the particular inputsignal. The camera trigger signal 44 preferably includes selected camerasetup information, including but not limited to the startline andendline of the region of interest (ROI), exposure time of the image tobe acquired, and mode of operation. The particular mode of operation ofthe illustrated system 16 designates the operational sequence andparameters of the camera 16. Representative modes of operation aredescribed in greater detail below. This camera setup information istypically communicated between the host processor 120 and acquisitionboard 14 by the PCI bus 100. The camera loader 42 further communicateswith selected memory blocks, illustrated as camera setup storage block48 and proximate register storage block 52, the functions of which aredescribed in further detail below.

[0064] The host processor 120 initializes the image acquisition system10 by storing selected setup information. This set up informationincludes mode of camera operation, regions of interest within the image,and exposure times. The host processor 120 further provides additionalsetup requirements for the camera 16. These include image buffers that aparticular client uses to receive, hold and process image data. The hostprocessor can select a particular region of interest within the imagecaptured by a camera 16 by specifying the line and pixel number of theupper left corner of the rectangular region of interest, and byspecifying similar information concerning the lower right-hand corner ofthe region of interest. The host computing system thus defines,according to simple calls, the region of interest for a selected frame.This selected region of interest can remain constant or can be changedeither after each frame or after a selected number of frames.

Image Acquisition

[0065] Referring again to FIG. 2, the camera trigger signal 44 generatedby the camera loader 42 for a particular camera 16 is loaded into theprogrammable imager controller 20 of that camera 16. The camera triggersignal 44 can be transmitted to the camera at any time and without theneed to have a destination address already allocated for the image to beacquired. If the image is acquired before a destination address can bemade available, the image data can simply wait at one or more locationson the data path, such as in a data FIFO 94, until a destination addressbecomes available, as described below.

[0066] According to the illustrated embodiment, the camera triggersignal 44 for a selected camera 16 is generated by the camera loader 42in response to the instructions stored in the camera setup store 48 forthat camera and in response to the output signal 53 of the proximityregister store 52. Specifically, the camera loader 42 accesses theinstructions stored in the camera setup store 48 for the selected camera16 and shifts the appropriate bits to the camera. The camera triggersignal 44 is preferably a signal that includes: w bits designating theexposure time, x bits designating the first line of the region ofinterest, y bits designating the number of lines in the region ofinterest, and z bits designating the camera mode for this shot. Thenumbers w, x, y and z depend on the CCD array circuit 54 of the camera16.

[0067] The camera trigger signal 44 can be different for each imageacquisition. As a result, it is possible to change the contents of thecamera setup store 48 at each frame. This enables the machine visionsystem to change exposure time, region of interest, or camera modebetween frames. Because image acquisition can proceed independently ofimage transfer, a change in the contents of the camera setup store 48has no appreciable impact on system performance.

[0068] The processes of image acquisition and memory allocation for theimage can be performed in parallel with and substantially independentlyof each other. This enables the system's memory manager to generatedestination addresses as system requirements dictate. Among theadvantages of this feature are that it enables the system: to acquire animage almost immediately after a request for an image is issued andwithout the often unpredictable latency associated with waiting for adestination address; to queue several image acquisition requests; and toperform time-consuming image processing tasks, for example writing it toa disk, independently of image acquisition and transfer. Hence, imageacquisition can be initiated without regard to the allocation of adestination address, which is eventually stored in memory 90.

[0069] In one instance, the programmable imager controller 20 preferablyincludes a programmable logic device such as a field programmable logicarray circuit (FPLA) and a voltage converter for transforming selectedsignals into a form compatible with the remaining camera components.Those of ordinary skill in electrical engineering and circuit designwill understand that the FPLA is an ASIC chip that can be designed tooperate in a manner in accordance with the teachings of the presentinvention.

[0070] The illustrated programmable imager controller 20 is programmablein that the receipt of a different camera trigger signal 44 at anyselected time, e.g., after each frame exposure or after any selectednumber of frame exposures, initiates a different image capturing scheme.For example, the camera 16 can be instructed, via the programmableimager controller 20, to transmit a different region of interest aftereach frame. This provides for a relatively simple method of dynamicallycontrolling the region of interest and exposure without requiring theuse of complex image capturing and processing circuitry. Furthermore,this programming is performed relatively rapidly. For example, in lessthan about 12 μs and preferably less than about 1 μs, the programmableimager controller 20 can generate a new set of instructions to the CCDarray circuit 54.

[0071] According to a preferred practice, the arrival of the last bit inthe programmable imager controller 20 arms the camera 16. subsequently,the camera loader 42 generates a camera trigger signal 21 that istransferred to the image capturing portion of the camera 16, whichincludes a CCD array circuit 54, an image processor 60, and anoscillator 58 local to the camera. The illustrated camera oscillator 58preferably transmits a camera timing signal 58B to the programmableimager controller 20 and to the acquisition board 14. This camera timingsignal 58B synchronizes the acquisition board 14 with the camera 16 andwith the host computing system 12. Those of ordinary skill in computerand electrical engineering will recognize that the camera triggersignals can be loaded in other ways.

[0072] Once the programmable imager controller 20 receives the cameratrigger signal 21, the CCD array circuit 54 initiates the exposureprocess according to the teachings of the present invention. Thisexposure process preferably lasts for a selected exposure period, asdefined by the selected exposure bits which comprise part of the cameratrigger signal 44 generated by the camera loader 42.

[0073] The system 10 runs kernel level software which is responsive tothe presence of the camera trigger signal 21 or a trigger signal on theexternal trigger inputs 36. Upon the occurrence of either of thesesignals, the kernel level software requests the system time from thehost processor 120. This request is set to have priority sufficientlyhigh to ensure negligible latency in the response of the host processor120. The system time is then made available for associating with theimage data acquired in response to the trigger signal.

Transmitting the Acquired Image Out of a CCD Array

[0074] The programmable imager controller 20 receives a camera triggersignal 21 representative of selected image capturing parameters. Thissignal is received by the CCD array circuit 54. The receipt of thistrigger signal initiates a sequence of signals for the control of asolid state imager such as a CCD array. The mechanism used by the CCDarray to deliver an image does not affect the operation of theinvention. The illustrated CCD array circuit 54 in the preferredembodiment is an interline transfer CCD which includes a CCD sensorarray having a number of photosites corresponding to a selected numberof pixel locations and a progressive scan chip that provides for theshifting of acquired optical data into a vertical array of registers.For example, if the camera is designed for 640×480 resolution, thenthere exists a photosite array of 640 columns and 480 rows ofphotosites, i.e. a photosite behind each pixel. Those of ordinary skillwill appreciate that the CCD array functions as an integrator of lightover time, and need not be described in further detail herein.

[0075] Referring to FIG. 3A, in an interline transfer CCD, eachphotosite 70 accumulates charge corresponding to that portion of theimage to which it is exposed. At the expiration of the exposure time andin response to the imager controller 20, each photosite 70 transfers itsstored charge to a shadow register 80 a in a vertical array of registers80 associated with the column of photosites. This transfer occurssimultaneously for all photosites in the array. Although FIG. 3A showsonly two columns of photosites and two vertical arrays of registers,those of ordinary skill will appreciate that for a 640×480 resolutionthere can exist 640 vertical registers.

[0076] Referring to FIG. 3B, in a frame transfer CCD, each photosite 70a accumulates charge corresponding to that portion of the image to whichit is exposed. At the expiration of the exposure time and in response tothe imaging controller 20, each photosite 70 a transfers its storedcharge to an adjacent photosite 70 b. The photosite at the edge of theCCD array 70 g transfers its charge to the topmost register 80 a in thevertical array of registers 80. This procedure is repeated until thecontents of the topmost photosite 70 a in a column of photosites 70 hasbeen shifted into the topmost register 80 a in the vertical array ofregisters 80.

[0077] It is apparent that the net result in both the frame transfer CCDof FIG. 3B and the interline transfer CCD of FIG. 3A is identical,namely a vertical array of registers 80 in which each register containsa charge corresponding to the charge held by a corresponding photosite.

[0078] The CCD array circuit 54 can further include a horizontal arrayof registers 82 having as many registers as there are vertical arrays ofregisters. Hence, for 640×480 resolution as in the example above, thehorizontal array of registers 82 would include 640 registers. Theregisters comprising the horizontal array of registers preferablycommunicate with the illustrated substrate surface 84. Although only onehorizontal array of registers is illustrated in the drawing, those ofordinary skill will appreciate that a number of horizontal arrays ofregisters can be used.

[0079] With further reference to FIGS. 3A and 3B, once the image hasbeen acquired by the camera and the charge associated with that imagehas been transferred to the vertical arrays of registers, theprogrammable imager controller 20 begins shifting the image data storedwithin the vertical arrays of registers 80 into the vertical array ofregisters 82. For a 640×480 image, the horizontal array of registers behorizontally shifted 640 times before the image transfer is completed.

[0080] In a conventional machine vision system acquiring an m×n image,at the end of each of the m shifts, the system 10 cannot decide whetherthe current line of registers corresponds to a line of the image withinthe region of interest. As a result, all the contents of all theregisters are transmitted to the acquisition board for furtherprocessing, regardless of whether or not the contents of the registerscorrespond to a line above or below the region of interest. Typically,it takes 50 to 100 times longer to discard the contents of the nregisters than it does to shift a row from the n vertical arrays ofregisters into the n registers in the horizontal array of registers. Asa result, in conventional systems, the rate at which an image can betransferred is limited by the rate at which the horizontal array ofregisters can be operated. Because of this, conventional systems fail toexploit the speed with which multiple lines of an image can be shiftedinto the horizontal array of registers.

[0081] In the system 10 of the present invention, at the end of each ofthe m shifts, the system can decide whether the contents of the nregisters correspond to a line of the image within the region ofinterest. If they do, the contents of the n registers are transmitted tothe acquisition board for further processing just as they were in theconventional system. However, if the contents of the n registers do notcorrespond to a line of the image within the region of interest, the nregisters are quickly overwritten by the next row of n registers fromthe n vertical arrays of registers. Any excess charge either simply“spills” into the substrate 84 with which, as set forth above, theregisters are in communication or is removed in one shift through thehorizontal register. As a result, the horizontal array of registers onlyhas to perform the slow process of transferring data to the acquisitionboard when a line from the region of interest has actually been loadedinto it. In this way, the present invention is able to exploit the speedwith which charge from the contents of the vertical array of registerscan be transferred to the horizontal array of registers.

[0082] The vertical array of registers 80 is shifted until the line ofinformation located immediately before the first line of the region ofinterest, as defined by the control bits generated by the camera loader42, is placed in the horizontal register 82. The next line is thenshifted vertically down, and then clocked horizontally out of thehorizontal register, to remove all charge therefrom.

[0083] The camera trigger signal 44 also includes the ending line of theregion of interest. Thus, the image data associated with each line ofthe region of interest is clocked into the horizontal register 82 andthen read out. This information is then transmitted to the imageprocessor 60, as denoted by CCD array output signal 59 and asillustrated in FIG. 2. The image processor 60 conditions the CCD arrayoutput signal 59 prior to transfer to the acquisition board 14. Theimage processor 60 is well characterized and known in the art and neednot be described further herein.

[0084] The remaining image data, if any, associated with the portion ofthe image outside the region of interest is then shifted out of thehorizontal and vertical arrays of registers 80, 82, and discarded. Thisis done by rapidly shifting the data from the array of verticalregisters 80 into the array of horizontal registers 82.

[0085] In addition to the method of fast vertical shifting through linesoutside the region of interest, further acceleration is achieved bytrading vertical resolution for speed within the region of interest. Themode word z above includes the number of adjacent lines to be combinedbefore each reading of the horizontal register during transfer of datawithin the region of interest. By this method two or more verticallyadjacent pixels are added together in the horizontal register and readout as one data value.

Operation of the Programmable Imager Controller

[0086]FIG. 4 and 5 illustrate in further detail the programmable imagercontroller 20 and camera 16 of the present invention. As shown, thecamera trigger signal 44 representative of camera control information istransmitted to the programmable imager controller 20, along with anyFIFO status signal 79, described further below, and the camera timingsignal 58B of the camera oscillator 58. In response, the programmablegenerator 20 produces a number of output signals, e.g., SD, V1, V2, V3,XFR, H1, H2, RG, Sh1, Sh2 ClpDm, IPOp, CB, and Cs, as well as an outputsignal that is transmitted to the image processor 60. The illustratedoutput signals communicate with an image processor 60, a CCD powerregulator 152, a vertical driver 156, and a CCD sensor array 160. TheCCD power regulator 152 converts the input signal 152B to a DC outputsignal 152A that communicates with the CCD sensor array 160 and with thevertical driver 156. To preserve data integrity, the charge pumping bythe CCD power regulator 152 is synchronized with the CCD sensor array160 so that the switching transients associated with the DC outputvoltage do not interfere with the transfer, storage or processing ofanalog image data.

[0087] The output signals V1-V3 cause the vertical driver 156 to driveor control the vertical shifting of the vertical array of registers 80.The signal SD initiates the purging of charge from the sensor array, asdescribed in further detail below. The output signals H1 and H2 drivethe horizontal array of registers 82 during operation.

[0088] The operation and use of the illustrated image processor 60, CCDpower regulator 152, vertical driver 156, and CCD sensor array would beobvious to the ordinary skilled artisan in the field of electricalengineering.

[0089] With reference to FIG. 5, the programmable imager controller 20of the present invention can be characterized by an illustrated statemachine 166 connected to a number of serially connected registers168-174, which load the camera trigger signals 44 generated by thecamera loader 42. The programmable imager controller 20 also includes ashift-in finished counter 176, and a shot-finished counter 178, avertical control generator 180, a horizontal control generator 182, anda CCD image processor signal generator 186.

[0090]FIG. 7 illustrates a flow chart schematic diagram of the statemachine and associated circuitry of the programmable imager controller20 of the present invention. During operation, the illustrated timinggenerator 20 waits for the next communication packet to be received, asillustrated in step 188. According to step 190, the communicationcomplete counter 176 is checked to see if it is equal to zero. If it isnot, the timing generator 20 continues to receive command data. If thecounter 176 is equal to zero, the appropriate counters are loaded withthe camera control information 44 designated by instruction bits x, y, zand w as illustrated in FIG. 5. The state machine 166 then produces aSIEN output signal 181A which is received by the vertical controlgenerator 180, according to step 194. In step 196, the exposure counter172 receives the vertical shift interval clock signal, and according tostep 198, the system checks to see if the exposure counter 172 is equalto zero. If it is, the exposure counter 172 is cleared, i.e., is nulled,as illustrated by step 200. The state machine 166 then toggles thesignal carried along 181B and received by the vertical control generatorbetween a logical high and a logical low, as illustrated by steps 202and 204. Thereafter, the state machine 166 generates a logic high along181A, as shown by step 206.

[0091] According to step 208 the shot-finished counter clock 178receives a vertical shift signal. According to step 210, the statemachine 166 generates logical highs along paths 181C and 181D.

[0092] In accordance with step 212, the ROI (region of interest) linecounter 170 is vertically shifted until this counter is zero, asillustrated by steps 214 and 216. At this time, the state machine 166sets the vertical clock's speed to a logical low along path 181D. Thisis received by the vertical control generator 180 (step 218).

[0093] The ROI last line counter 168 is likewise vertically shifteduntil the counter reaches zero, in accordance with steps 220 and 222.The state machine 166 then generates a logical high along path 181D. Theillustrated system then checks to see if the shot-finished counter 178is equal to zero. If so, the system produces logical lows along paths181C and 181D, as illustrated by steps 228 and 230. The programmableimager controller 20 then reloads the shot-finished counter, inaccordance with step 232. Those of ordinary skill will recognize thatthe block diagram schematic depiction of the programmable imagercontroller 20 in conjunction with the flow chart diagram illustratingthe operation thereof effectuate the vertical and horizontal clocking ofthe registers of the CCD sensor array, as well as effectuate the purgingof charge from the photosites of the CCD array.

[0094]FIG. 6 shows, in tabular format, the states of selected gates ofthe programmable imager controller during image acquisition andtransmission.

[0095] During image acquisition, the signals SIEN and XFREN cooperate toenable image exposure. SIEN drops to logical 0 to arm the camera forexposure. Note that SIEN does not trigger the exposure. Exposure beginswhen XFREN transitions from a logical 0 to a logical 1 and ends whenXFREN returns to its idle state at logical 0. Upon termination ofexposure, SIEN reverts back to a logical 1, thereby disarming thecamera.

[0096] During image transmission, VCKEN transitions to a logical 1 toarm the transmission of data from the camera to the acquisition board.For lines of image data forming part of the region of interest, thetransmission alternates between a fast shift step during which imagedata is vertically shifted one line at a time from the vertical array ofregisters to the horizontal array of registers and a readout step duringwhich the line of image data is shifted out of the horizontal array.VCKEN remains at a logical 1 throughout both of these steps.

[0097] Switching between the fast shift step and the slower readout stepis controlled by the signals VCKSP and HCKEN. During the fast shiftstep, VCKSP is set to logical 1. VCKSP drops to logical 0 to arm thereadout step. Note that VCKSP does not actually initiate the readoutstep. Readout begins when HCKEN drops to a logical 0 and ends when HCKENreturns to a logical 1.

Allocation of Memory for Storage of Acquired Image

[0098] As set forth above, the process of allocating memory for storageof an acquired image can occur independently of and concurrent withimage acquisition. This memory allocation method, which will be referredto as “hardware scatter/gather,” makes use of a modern operatingsystem's ability to perform dynamic memory allocation.

[0099] In hardware scatter/gather systems, the system's memory manager,upon request of a software application, will allocate memory for imagestorage. Once the memory is no longer needed for image storage, thememory manager can return the allocated memory to a common memory poolfor use in subsequent computing tasks. In this way, the system canallocate a different memory address to each frame and can allocate onlythe amount of memory necessary at any instant. Since memory allocationcan proceed concurrently with image acquisition, throughput of thesystem is improved and acquisition of an image can be triggered with aminimum of latency.

[0100] Dynamic memory allocation algorithms are available in many modernoperating systems. The use of such dynamic memory allocation is thuswell within the capability of one having ordinary skill in the art ofcomputer engineering.

Pixel Sensitivity Correction

[0101] With reference to FIGS. 2, 8A, and 8B, according to an optionalfeature of the invention, the image processor output signal 61 istransferred to a pixel sensitivity correction module 62 which multipliesthe output corresponding to each photosite 70 by a predetermined pixelsensitivity factor. This pixel sensitivity factor can compensate for thediffering response characteristics of each photosite 70 or for errorscaused by the inability to precisely control the scene illumination.Additionally, the multiplication of the output corresponding to eachphotosite 70 by its corresponding pixel sensitivity factor can result inspatial filtering of the acquired image. In this way, the pixelsensitivity correction module 62 can perform a preliminary imageprocessing step in real time without interrupting the host processor120. Since the preliminary image processing step performed by the pixelsensitivity correction module 62 would otherwise have to be performed bythe host processor 120, the presence of the pixel sensitivity correctionmodule 62 saves overall processing time and increases the throughput ofthe system.

[0102] Referring to FIG. 8A, the pixel sensitivity correction module 62comprises memory that stores a pixel sensitivity factor storage table63, which includes the pixel sensitivity factors and a multiplier 64.Additionally, the pixel sensitivity correction module 62 can include acounter 65 which rolls over at the number of pixels in the region ofinterest.

[0103] In the illustrated embodiment, the pixel sensitivity correctionmodule 62 is connected to the analog side of the A/D converter 74.However, the pixel sensitivity correction module 62 can also beconnected to the digital side of the AID converter 74, as shown in FIG.8B.

[0104] The output of the pixel sensitivity correction module isconnected to the analog input of an analog-to-digital (A/D) converter 74which converts the analog output signal of the camera to a digitalsignal. The construction of such converters is well known in the art ofelectrical engineering and suitable converters are commerciallyavailable. In one practice of the invention, the A/D converter 74 can bea component of the camera 16. In such a case, the pixel sensitivitycorrection module would be connected to the digital side of the A/Dconverter 74 as shown in FIG. 8B.

[0105] In operation, the pixel sensitivity correction module 62 acceptsdata from either the image processor 60 as shown in FIG. 8A or thedigital side of the A/D converter 74 as shown in FIG. 8B. In eithercase, the pixel sensitivity correction module uses its counter 65 todetermine which entry from the pixel sensitivity factor storage table 63corresponds to the pixel currently at the input to the pixel sensitivitycorrection module 62. The corresponding entry from this storage table isthen made available to the multiplier 64 which multiplies it by thevalue of the pixel currently at the input to the pixel sensitivitycorrection module 62. The product is then transmitted from themultiplier 64 to the analog input of the A/D converter 74 as shown inFIG. 8A and in FIG. 2 or to the data FIFO 78 as shown in FIG. 8B. Inmost embodiments, an adder precedes the multiplier 64. This addermodifies the pixel value by a unique offset correction stored inparallel with the sensitivity correction factors.

Data Transmission from the Data FIFO to the Host Computing System

[0106] Each camera 16 in the illustrated system 10 has associated withit a data FIFO 78 in which image data accumulates as it arrives from thecamera 16. This data FIFO 78 is periodically emptied by transmitting theaccumulated data stored within it to the memory location allocated forthat camera 16, the starting physical address and extent of which arestored in the destination address store 90. The data FIFO 78 isgenerally emptied when the amount of accumulated data reaches some dataFIFO threshold. The data FIFO 78 can be emptied of accumulated data attimes independent of the times at which data arrives at the data FIFO.For this reason, the data FIFO makes possible the asynchronous transferof data between the camera 16 and the host computing system 12. As usedherein, the term “data FIFO” is intended to include contiguous andnon-contiguous memory and registers, including FIFO and other memorytypes. The memory or register can form part of the memory of the hostdevice, or can be implemented in SRAM, DRAM, FLASH, or remote drives, oron other memory associated with a dedicated electrical circuit used inconjunction with the camera 16 and the host computing system 12 of theinvention.

[0107] This occurs when the acquisition board 14 performs a DMA (directmemory address) transfer of the data to the address locations defined inthe camera destination address store 90. The camera destination store 90is preferably preloaded with an appropriate address definitions by thehost processor 120 of the host computing system 12.The choice of thisdata FIFO threshold is important for the efficient and economicalfunctioning of the system. If the data FIFO threshold is chosen toohigh, it becomes necessary to use data FIFO's having sufficient capacityto store the data. Such high capacity data FIFO's can be prohibitivelyexpensive. If, on the other hand, the data FIFO threshold is too low,the system 10 will have to frequently access each FIFO, retrieving onlya small amount of data therefrom. This is an inefficient use of systemresources.

[0108] In the illustrated embodiment, the image acquisition performed bythe camera 16 can be conveniently interrupted between the end of oneline of the image and the beginning of the next line. Thus, a convenientdata FIFO threshold is a single line of the image. However, theinvention is not restricted to the use of a single line of the image asthe data FIFO threshold.

[0109] The transmission of image data from the data FIFO 78 to the hostmemory 116 proceeds until the last line of data corresponding to theselected region of interest has been transmitted. The accumulated dataretrieved from the data FIFO 86 is transferred to the PCI bus 100through the bus interface 102 and then transferred through the IO mangerto host memory, significantly reducing the number of times the hostprocessor 120 is interrupted, thus increasing the processing speed andefficiency of the overall system 10. The co-processor 124 alsocommunicates with the memory bus 110. Prior systems utilize the hostprocessor 120 to perform each data transfer thereby requiring that theprocessor be interrupted for each data transfer. The present inventionovercomes this drawback by using DMA to move relatively large blocks ofimage data, thereby significantly reducing the number of host processorinterrupts. According to a preferred practice, the IO manager 120 isinterrupted during acquisition of the region of interest. The softwarestored in the host computing system, e.g., cam.dll, calculates thenumber of pixels received from the region of interest and transmits thetrigger threshold parameters to the proximity evaluator 88. Theparameters transmitted to the proximity evaluator 88 preferably define asummary statistic for a portion of the region of interest whose valuesare monitored to determine when the object whose image is to be capturedis present in the camera's field of view. The pixel value containedwithin proximity evaluator 88 is then compared with a preselected valuestored in the proximity register store 52. When this value is reached,the proximity evaluator 88 generates a proximity evaluator output signal88A that is transferred to the camera loader 42. In response, the cameraloader generates another set of instructions which are transferred tothe programmable imager controller 20.

Interruption of Data Transfer

[0110] A significant advantage of the image acquisition system 10 of theinvention is that it compensates for the unpredictable delays intransferring image data from the camera 16 through the acquisition board14 to the memory 128 of the host computer. This is accomplished by thereal-time interruption, for a selected period of time, of datatransmission by each camera, before data path overflow occurs. Any dataalready acquired by the camera 16 but not yet transmitted to theacquisition board 14 is stored in the camera's own storage facility,e.g., in the vertical array of registers 80, for the duration of theinterruption period. This provides for a cost-effective method ofstoring the untransferred portion of an image.

[0111] Data transmission from the camera 16 can be interrupted asfrequently as necessary. Moreover, interruption can occur not onlybetween frames but at the conclusion of transmission of any preselectedsubset of the frame. For example, according to one practice,interruption can occur between the end of one line and the beginning ofthe next line. This is advantageous since data traffic on the hostcomputing system 12 is an unpredictable function of all the activity inthe system, much of which is often unrelated to the transfer of imagedata. Systems lacking a reliable method of managing data traffic canfail to provide the high fidelity data transmission required by machinevision and other image processing systems. For example, prior systemsare known to randomly drop lines or even large portions of a frame ofimage data. In machine vision applications, this loss of image data canresult in improper functioning of the system.

[0112] With further reference to FIG. 2, while the acquisition board 14is performing this DMA data transfer, additional image data continues tobe read into the data FIFO 78. This data is bundled together andtransferred to the next address location unless other traffic on thehost computer's I/O bus 100 delays this transfer. In the event that bustraffic prevents the transfer long enough for more than an arbitrarilylarge fraction of the data FIFO to be filled, a data FIFO status bit 79is asserted and transmitted to the camera 16. If the data FIFO statusbit 79 is received by the programmable imager controller 20, theprogrammable imager controller 20 interrupts data transfer byinterrupting the next vertical shifting of data into the vertical arrayof registers 80 and, optionally, by interrupting the read-out of imagedata from the horizontal array of registers 82. This interruption isadvantageous since it ensures that no amount of acquired optical data islost, e.g., a dropped line or frame, due to data traffic in the hostcomputing system. The data FIFO status bit 79 provides for a feedbackloop between the acquisition board 14 and the programmable imagercontroller 20 for sensing data overflow. In response to thisinterruption, the camera 16 retains the data within the CCD verticalregisters 80 for as long as necessary for the host computing system 12to resume accepting DMA transfers. This feedback process results in ahighly reliable and cost effective image acquisition system in which theacquisition hardware itself is used to temporarily store the acquiredimage data. Furthermore, through this interruption feature and itsassociated feedback loop, the invention maintains the integrity of theacquired data and nearly eliminates the loss or corruption of data dueto unpredictable latency periods in performing DMA transfers.

[0113] A transfer-complete interrupt is communicated via the host to theclient executable when the programmable imager controller 25 signalsthat all pixels from the region of interest have left the camera head16, and the value of FIFO status_(x) 79 indicates that the Data FIFO isempty. This interrupt is preferably generated after the last byte ofimage data has been flushed through the system.

Purging the CCD Array

[0114] After the transfer gate of the CCD array is restored to itsnormal status, the programmable imager controller 20 sends a continuingset of pulses to the CCD array circuit 54 to purge the photosites of anyaccumulating charge until the next exposure. This ensures that unwantedoptical data is neither stored nor processed by the acquisition system10. This purging process preferably continues in parallel with otheroperations until the next exposure command is generated by the cameraloader 42 the camera is operating in pipelined exposure mode.

[0115] Referring to FIG. 4, to purge the CCD array, the programmableimager controller 20 transmits the signal SD to the vertical driver 156.This causes the vertical driver 156 to rapidly shift the contents of thevertical array of shift registers 80 into the horizontal array of shiftregisters 82. This rate at which data is shifted from the vertical arrayof shift registers 80 into the horizontal array of shift registers 82 istypically much faster than the rate at which the horizontal array ofshift registers can be shifted horizontally. However, since purgingoccurs only when the data in the vertical array of shift registers is ofnot interest, the corruption of data in the horizontal array ofregisters is unimportant.

Transmission from the VGA FIFO to the Video Display

[0116] The digital data signal 75 of the A/D converter 74 is alsotransferred to a display FIFO 94. The display FIFO 94 stores the imagedata for subsequent processing and display on a display monitor (notshown). The digital data signal 75 from by the A/D converter 74 isconverted to a signal suitable for the display monitor by the lookuptable (LUT) 96. The destination address for the data stored in thedisplay FIFO 94 is stored in the display destination address store 108.The address store holds the storage address of the memory location towhich the acquired data is to be transferred. As used herein, the term“display FIFO” is intended to include any appropriate memory locationthat can store data in selected byte sizes.

[0117] Another advantage of the present invention is that it does notuse phased lock loops. Phase locked loops are prone to timing errorswhich can result in pixel jitter and skew. Consequently, the imageacquisition system of the present invention reduces pixel jittersubstantially to zero. Moreover, the absence of phase locked loopssimplifies the data path and reduces system cost.

Modes of Operation

[0118] The image acquisition system of the present invention has severalmodes of operation. According to a triggering mode, the imageacquisition system can be externally triggered. This can occur when atrigger from machinery external to both the camera 16 and the hostcomputing system 12 sends a signal (typically a signal having an edge)to an external trigger interface 34 having n inputs, one for each of thecameras connected to the system. The arrival of the pulse edge on one ofthe external trigger inputs 36 triggers the camera loader 42 to generateand to transfer a camera trigger signal 44 to the camera 16 designatedby the particular external trigger input 36. The camera trigger signal44 is then transferred to the programmable imager controller 20 for theselected camera 16.

[0119] At the expiration of the preselected exposure time, theprogrammable imager controller 20 initiates a charge transfer from thephotosites 70 of the CCD array circuit 54 to its vertical array ofregisters 80. The image data representative of the region of interest isthen clocked out of the vertical array of registers 80 and into thehorizontal array of registers 82. Image data from outside the region ofinterest is clocked out of the vertical registers and into thehorizontal array of registers 82 at speeds significantly greater thanthe speed at which data can be clocked out of the horizontal register.This selectively fast “dumping” of unwanted image data allows the system10 to access and to obtain relatively quickly the image datacorresponding to the region of interest. The acquired image data thatresults from overwriting the data in the horizontal array of registersis ignored.

[0120] After the transfer gate of the programmable imager controller 20is restored to its normal status, the imager controller transfers a setof pulses to the CCD array circuit 54 that causes the CCD tocontinuously extract charge building up in the photosites of the array.This process preferably continues in parallel with other operationsuntil the exposure for the next image begins.

[0121] For the number of lines in the region of interest, theprogrammable imager controller 20 drives the CCD array circuit 54 at arate that provides uncorrupted image data to the computing host system12. The image data is conditioned in the camera 16 by the imageprocessor 60 after which it is transferred to the acquisition board 14.The acquisition board 14 can include a pixel sensitivity correctionmodule 62 for multiplying each pixel of the image by a predeterminedpixel sensitivity factor and collects the resulting image data in thedata FIFO 78 until the amount of accumulated data reaches a threshold.The acquisition board 14, in conjunction with the host computing system12 then performs a DMA transfer (a data burst) of the accumulated datato the address defined in the camera destination store 90. Theseaddresses preferably correspond to the first physical block of memory ofthe currently specified image buffer. Data continues to be read into thedata FIFO 78 even during the DMA transfer.

[0122] When the data in the data FIFO 78 again accumulates past thethreshold, another DMA transfer is made to the next starting address,unless bus loading by other data traffic on the host computer's I/O busdelays this transfer. In the event that bus traffic prevents thetransfer of data long enough for more than half of the data FIFO to befilled, the data FIFO status bit is asserted. When this occurs, the dataFIFO's associated camera suspends data acquisition and transmission andholds any already acquired data within the vertical array of registers80 of the CCD until the host computer can resume accepting DMAtransfers. This process proceeds until the last line of the region ofinterest is transmitted to the memory of the host computing system 12.

[0123] When the last line of the region of interest is read or shiftedout of the horizontal register, the programmable imager controller 20generates a “fast shift” signal which instructs the CCD array 54 to dumpall remaining data associated with the originally acquired image. Thisdata purge is accomplished in the manner described above. At this pointpreferably all of the vertical array of shift registers 80 are free ofcharge. All of the photosites 70 are also preferably empty since thetiming generator 20 pulses the CCD array 54 such that the array removesany charge from the photosites 70. In this way, the camera 16 is readyto receive another image acquisition command.

[0124] Once all DMA transfers of image data are completed, the hostcomputing system 12 responds to the controller's 14 activation of one ofthe interrupt lines on the host's I/O bus to trigger the processing ofthe interrupt code, i.e. cam.VxD 137, that was loaded by the cam.exeprogram 132 at boot time. The interrupt code 137 makes a call-back tomemory maintained by cam.dll 138 that stores the handle of the processthat client.exe (or cam.exe) has most recently designated to receivenotice that a particular image buffer has been filled with new data.

[0125] According to another mode of operation referred to as “immediatemode,”, the image acquisition system of the invention can be used toaccommodate both image analysis and machine vision applications. In thismode of operation, data resulting from processing an earlier imagedictates the next action to be taken.

[0126] Accordingly, in this mode, the acquisition board 14 waits for acommand from the host to be written before initiating an imageacquisition and processing cycle similar to that described above. Eitherclient.exe 134 or cam.exe 132 makes a call to cam.dll 138 to have thecommand transmitted. The arrival of this command causes the cameraloader 42 to transmit the camera trigger signal 44 containinginformation from the camera setup store 48 to the particular cameradesignated by that byte. The remaining steps of image acquisition andtransfer proceed as described above.

[0127] According to still another mode of operation, images can be takenat fixed time intervals from a selected camera. These time intervals toselected and can be any value greater than or equal to the minimum timecompatible with the selected exposure time and the time required totransfer the region of interest. This mode of operation is identical tothat described immediately above with the exception that the trigger forinitiating image acquisition by the selected camera is an associatedtimer forming part of the camera loader 42.

[0128] In this mode, either cam.exe 132 or client.exe 134 makes a callto cam.dll 138 that sends a command to the host computing system 12and/or the acquisition board 14. This command includes a particulartarget camera and a data word used to set the associated timer in thecamera loader 42. Every time the timer for the selected camera timesout, the camera loader 42 sends a camera trigger signal 44 to beginacquisition by the selected camera.

[0129] In response, an image is returned from the selected camera 16 andtransferred to host memory 116, each time that the timer associated withthat camera times out.

[0130] According to yet another mode of operation, the image acquisitionsystem provides for continuous image acquisition at a rate constrainedonly by the size of the region of interest and the exposure time. Thismode begins with a request by cam.exe 132 or client.exe 134 thatparticular camera setup information be sent from the camera setup store48 to a particular camera 16 via the host interface of the acquisitionboard 14. The camera setup information causes the camera 16 to initiatean exposure and readout of image data, as set forth above in relation tothe description associated with FIGS. 1-3. The camera's response in thismode differs in that after exposure is complete, the programmable imagercontroller 20 does not immediately pulse the CCD array 54 to clear thephotosites of charge.

[0131] According to one preferred practice, if cam.dll 138 calculatesthat an exposure time longer than the readout time for the region ofinterest, then the camera setup information contained in the cameratrigger signal 44 causes the programmable imager controller 20 to beginthe next exposure immediately after the transfer of the image data. Theforegoing purging of charge from the photosites does not occur since thenext exposure taken by the camera 16 continues while the vertical arrayof registers 80 containing the image data from the previous exposure isread into the horizontal array of registers 82. The acquisition ofadditional frames continues beyond the end of the readout of thepreviously acquired data, until the appropriate exposure time isreached. At this time, the timing generator 20 commands a “frametransfer,” and begins both another exposure and another readout. Theprocess repeats until new camera setup information is transmitted to thecamera 16 from the camera setup store 48.

[0132] If, on the other hand, cam.dll 138 calculates a readout time forthe region of interest longer than the exposure time, then the camerasetup information contained in the camera trigger signal 44 causes theprogrammable imager controller to begin purging charge from thephotosites after a frame transfer and to continue to purge charge for atime interval as long as the excess of the readout-time overexposure-time. When the image transfer is completed, the programmableimager controller 20 initiates another “frame transfer,” resumes chargepurging, and begins another readout. This process continues until newcamera setup information is transmitted from the camera setup store 48to the camera 16.

[0133] In the event that FIFO status signal 79 is asserted for longenough to substantially affect the exposure during a cycle, theprogrammable imager controller 20 terminates the readout of image datafor that cycle. Readout resumes at the beginning of the region ofinterest for the data then in the photosite region.

[0134] According to still another mode of operation, the system 10 canrecognize when a subject of interest is within a triggering region 95 inthe camera's field of view as shown in FIG. 9. Upon recognizing that asubject of interest has entered the triggering region 95, the systemautonomously triggers the capture of a region of interest 99, also shownin FIG. 9, within the cameras field of view and transmits the image datacorresponding to that region of interest to the system's memory and/orto the system's display. The size and location of the triggering region95 is independent of the size and location of the region of interest 99.This mode greatly facilitates automated image processing by allowing theuser or client software to adaptively control, based on the presence ofan object in the field of view, when image acquisition will occur.

[0135] This mode of operation is similar to the immediately precedingmode. Generally, the camera trigger signal 44 will include one or morethresholds which will be used by the acquisition board to determinewhether an image of the region of interest should be acquired. Thesethresholds are previously calculated by cam.dll 138 and loaded into thecamera setup store 48. In addition, the camera trigger signal 44 cancontain information necessary to define a triggering region in a mannersimilar to that used and already described for defining the region ofinterest.

[0136] In this mode, the trigger region is repeatedly captured andtransmitted to the acquisition board 14 according to the procedureidentified above for transmitting image data to the acquisition board.However, rather than being routed, as in the other modes, to the dataFIFO 78, image data from the triggering region is sent to the proximityevaluator 88 which accumulates the values of the pixels arriving fromthe triggering region. Upon completion of the transfer of the triggerregion for a given frame, the summary statistics of the pixels from thetrigger region, now stored in the proximity evaluator 88, is used todetermine whether the image from the region of interest should becaptured. If the system determines that the accumulated value is suchthat the image from the region of interest should be captured, then thatimage is routed to the data FIFO 78 as described earlier. If, on theother hand, the system determines that the accumulated value is suchthat no image from the region of interest should be captured, thenanother trigger region is captured, accumulated and compared.

[0137] Whether or not to acquire an image from the region of interest 95based on the image in the trigger region 99 can depend on the sum of thevalues of the pixels in the trigger region or on the deviation of thevalues of the pixels in the trigger region.

[0138] In one implementation of this mode, whether or not an image fromthe region of interest is captured can depend on whether the accumulatedvalue of the pixels in the trigger region is above or below a threshold.In a second implementation of this mode, there can be n thresholds andthe capture of an image from the region of interest can be conditionedon which of the n+1 intervals defined by the n thresholds theaccumulated value of the pixels from the trigger region falls into. In athird implementation of this mode, the capture of an image from theregion of interest can be conditioned on whether or not the deviation ofthe summary statistics of the pixels from the trigger region from somenorm falls above or below a programmed deviation threshold. Furtherimplementations of this mode can be obtained by various booleancombinations of the above conditions.

[0139] The acquisition of an image from a region of interest can also beconditioned on the satisfaction of a-temporal condition. For example,the system can be made to acquire an image from the region of interestonly when the time interval between the proposed acquisition and thelast acquisition is in excess of some temporal threshold. A temporalcondition such as this can be combined with the conditions onaccumulated pixel values and deviations as outlined above. Absent such afeature, an extended and homogenous object slowly traversing thecamera's field of view could result in multiple exposures of the sameobject.

[0140] In yet another mode of operation, an image from one cameraoperating in the mode immediately above can trigger image acquisitionand transfer by another camera connected to the system.

[0141] In yet another mode of operation, the camera loader generatesoutputs, synchronized to each camera, to trigger eternal illuminationsystems such as flash units.

[0142] It will thus be seen that the invention efficiently attains theobjects set forth above, among those made apparent from the precedingdescription. Since certain changes may be made in the aboveconstructions without departing from the scope of the invention, it isintended that all matter contained in the above description or shown inthe accompanying, drawings be interpreted as illustrative and not in alimiting sense.

[0143] It is also to be understood that the following claims are tocover all generic and specific features of the invention describedherein, and all statements of the scope of the invention which, as amatter of language, might be said to fall therebetween.

Having described the invention, what is claimed as new and desired to besecured by Letters patent is:
 1. A system for transmitting an image to amachine vision system having a host processor that allocates memory forstorage of said image, said system comprising: image acquisition meansfor acquiring at least a portion of said image in response to a triggersignal, memory means for storing data representative of said image,image transfer means for transferring said image from said imageacquisition means to said memory means, said image transfer meansincluding buffer memory means for temporarily storing said at least aportion of said image pending allocation of memory space from saidmemory means by the host processor, wherein said image acquisition meanscan operate substantially independently of the allocation of memory bythe host processor.
 2. A system according to claim 1, wherein saidbuffer memory means comprises a data FIFO register, said data FIFO beingcoupled to receive data representative of said image from said imageacquisition means and to release data representative of said image tothe host processor in response to a release signal.
 3. A systemaccording to claim 1, wherein said buffer memory means comprises aplurality of registers, said plurality of registers being coupled toreceive data representative of said image from said image acquisitionmeans in response to said trigger signal and to release datarepresentative of said image to the host processor in response to arelease signal.
 4. A system according to claim 1, wherein said imageacquisition means comprises photo-sensitive means for acquiring saidimage in response to said trigger signal containing selected imageacquisition parameters, and programmable control means in circuit withsaid photo-sensitive means for generating said trigger signal and forprogrammably altering during acquisition of said image said selectedimage acquisition parameters.
 5. A system according to claim 4, whereinsaid photo-sensitive means includes a CCD array and said programmablecontrol means includes a programmable imager controller.
 6. A systemaccording to claim 4, wherein said programmable control means comprises:a controller adapted to be programmed with said selected imageacquisition parameters and for generating said trigger signal inresponse to a loading signal, and parameter loading means coupled tosaid controller for generating said loading signal and for receivingsaid image acquisition parameters.
 7. A system according to claim 4,wherein said programmable control means includes a programmable imagercontroller circuit; said controller circuit being adapted to beprogrammed with said image acquisition parameters.
 8. A system accordingto claim 7, wherein said programmable imager controller circuit includesmeans for receiving said image acquisition parameters in less than orequal to about 2 μs.
 9. A system according to claim 7, wherein saidprogrammable imager controller circuit includes means for reprogrammingsaid circuit on the fly, in essentially real time.
 10. A systemaccording to claim 7, wherein said programmable imager controllercircuit operates at a driving frequency, said programmable imagercontroller circuit comprising means for automatically changing saiddriving frequency during acquisition of said image.
 11. A systemaccording to claim 6, further comprising actuation means for generatingan output actuation signal in response to an input command signal, saidparameter loading means generating said loading signal in response tosaid actuation signal, and parameter memory means, in communication withsaid parameter loading means, for receiving said image acquisitionparameters from the host processor.
 12. A system according to claim 4,wherein said image acquisition means further includes actuation meansfor generating an output actuation signal in response to a commandsignal, parameter memory means in communication with said programmablememory means for receiving said image acquisition parameters from thehost processor, and a camera loader circuit adapted to receive saidselected image acquisition parameters from said parameter memory meansand said output actuation signal, for programming said programmablecontrol means with said image acquisition parameters.
 13. A systemaccording to claim 4, wherein said buffer memory means comprises one ormore vertical registers coupled to said photo-sensitive means forstoring optical energy representative of said acquired image, and one ormore horizontal registers positioned to receive at least a portion ofsaid optical energy stored in said vertical register.
 14. A systemaccording to claim 13, wherein said photo-sensitive means is adapted toacquire a region of interest corresponding to at least a portion of saidimage, and wherein said means for transferring tranfers a portion ofsaid optical energy corresponding to a portion of said region ofinterest from said vertical register into said horizontal register,further comprising disabling means for disabling transfer of saidoptical energy from said horizontal register during said transfer ofoptical energy from said vertical register into said horizontalregister, whereby said optical energy corresponding to a portion of saidregion of interest is rapidly transferred from said vertical register tosaid horizontal register without actively removing said stored energyfrom said horizontal register.
 15. A system according to claim 14,wherein said photo-sensitive means is adapted to acquire a region ofinterest corresponding to at least a portion of said image, and whereinsaid means for transferring tranfers a portion of said energy stored insaid vertical register corresponding to a portion of said region ofinterest into said horizontal register, further comprising enablingmeans for enabling transfer of said optical energy stored in saidhorizontal register therefrom, and disabling means for disablingtransfer of optical energy from said vertical register into saidhorizontal register during said transfer of optical energy out of saidhorizontal register.
 16. A system according to claim 2, furthercomprising direct memory address data transfer means for transferringsaid image data accumulated in said data FIFO register directly memoryallocated in the host computing system, whereby said data tranfersubstantially reduces the number of times said system interrupts thehost processor.
 17. A system according to claim 2, further comprisingpre-processing means separate from the host processor for receiving saidimage data and for at least partially processing said data withoutsubstantially interrupting the host processor.
 18. A system according toclaim 2, further comprising interrupt means coupled to said data FIFOregister and to said image acquisition means for interrupting saidacquisition of said image when said data FIFO register is at leastsubstantially full, thereby permitting reliable transfer of datacorresponding to said image.
 19. A system according to claim 18, whereinsaid image is composed of a plurality of lines, and wherein saidinterrupt means is capable of interrupting said acquisition of saidimage between said lines corresponding to said image.
 20. A systemaccording to claim 2, further comprising feedback means coupled betweensaid image acquisition means and said data FIFO register for monitoringsaid status of said register and for transferring an interrupt signal tosaid image acquisition means to interrupt said acquisition of saidimage, said feedback means including interrupt means coupled to saiddata FIFO register for generating said interrupt signal when said dataFIFO register is at least substantially full, whereby said interruptmeans immediately and temporarily interrupts said acquisition of saidimage.
 21. A system according to claim 1, wherein said image acquisitionmeans acquires said image in parallel with and substantiallyindependently of allocation of memory by the host processor.
 22. Asystem according to claim 1, wherein said image acquired by said imageacquisition means includes a plurality of pixels, further comprisingpixel correction means in circuit with said image acquisition means forcorrecting said pixels prior to transfer to said memory means.
 23. Asystem according to claim 22, wherein said pixel correction meanscomprises second memory means for storing a plurality of pre-determinedpixel correction values corresponding to each pixel of said image, andmultiplier means for multiplying each pixel of said image by saidcorresponding pixel correction value, thereby forming a corrected pixel.24. A system according to claim 22, wherein said pixel correction meansis separate from the host processor and performs said pixel correctionin real time.
 25. A system according to claim 4, wherein said image hasa region of interest corresponding to a portion of said image, saidregion of interest having a selected number of pixels, furthercomprising pixel evaluation memory means coupled to image acquisitionmeans for storing a value corresponding to said selected number ofpixels,and pre-determined pixel storage means coupled to said imageacquisition means for storing a value corresponding to a predeterminednumber of pixels.
 26. A system according to claim 25, further comprisingcomparing means for comparing said value stored in said pixel evaluationmeans with said value stored in said pre-determined pixel storage means,and means for generating a match signal when said values are equal, saidprogrammable control means including means for receiving said matchsignal and for altering said image acquisition parameters.
 27. A machinevision system for acquiring an image, said system comprising: imageacquisition means for acquiring said image, said image acquisition meansincluding means for altering image acquisition parameters prior toacquisition of said image; memory means for storing said image; imagetransfer means for transferring said image from said programmable imageacquisition means to said memory means, said image transfer meansincluding means for interrupting transfer of said image at aninterruption point, and means for resuming transfer of said image fromsaid interruption point. whereby resuming said acquisition of said imageat said interruption point substantially prevents loss of datacorresponding to said image.
 28. A system according to claim 27, whereinsaid image acquisition means includes means for defining at least oneregion of interest, said at least one region of interest being a subsetof said image, and means for acquiring said at least one region ofinterest.
 29. A system according to claim 28, wherein said at least oneregion of interest is a rectangular region of interest having a firstcomer and a second comer diagonally opposite said first corner, said atleast one region of interest being defined by the coordinates of saidfirst comer and the coordinates of said second comer.
 30. A systemaccording to claim 27, wherein said image acquisition means comprisesmeans for programmably controlling the amount of optical energycorresponding to said image collected by a camera.
 31. A systemaccording to claim 27, wherein said image acquisition means includestrigger means for initiating acquisition of said image in response to atrigger signal.
 32. A system according to claim 27, wherein said imageacquisition means includes a camera.
 33. A system according to claim 27,wherein said image acquisition means includes image correction means formultiplying a subset of said image by a correction value correspondingto said subset of said image.
 34. A system according to claim 33,wherein said image correction means comprises image input means foraccepting data representative of said image, storage means for storingsaid correction factor corresponding to said subset of said image, saidstorage means having input means responsive to an external signal,multiplier means coupled to said storage means and coupled to said imageinput means for multiplying said correction value with saidcorresponding subset of said image, and data counter means coupled tosaid storage table means for determining correspondence between saidsubset of said image and said correction value.
 35. A system accordingto claim 27, wherein said image acquisition means includes means forencoding an acquisition time into said image.
 36. A system according toclaim 27, wherein said means for encoding an acquisition time into saidimage comprises kernel level software in communication with a hostprocessor, said kernel level software being responsive to a cameratrigger signal.
 37. A system according to claim 27, wherein said imagetransfer means includes a data FIFO memory for storing data and forreleasing data asynchronously.
 38. A system according to claim 27,wherein said image transfer means includes programmable imager datatransfer means for selectively controlling the rate at which datatravels from said image acquisition means to said memory means.
 39. Asystem according to claim 38, wherein said programmable imager transfermeans comprises first data storage means for storing said image acquiredby said image acquisition means, second data storage means coupled tosaid first data storage means, first shift means for shifting a subsetof said image stored in said first data storage means to said seconddata storage means thereby storing said subset of said image in saidsecond data storage means, second shift means for shifting said subsetof said image stored in said second data storage means to said memorymeans, and disable means for disabling said second shift means duringoperation of said first shift means and to disable said first shiftmeans during operation of said second shift means.
 40. A systemaccording to claim 27, wherein said image transfer means comprises firstdata storage means for storing said image acquired by said imageacquisition means, second data storage means coupled to said first datastorage means, first shift means for shifting a subset of said imagestored in said first data storage means to said second data storagemeans thereby storing said subset of said image in said second datastorage means, second shift means for shifting said subset of said imagestored in said second data storage means to said memory means, anddisable means for disabling said second shift means during operation ofsaid first shift means and to disable said first shift means duringoperation of said second shift means, said disable means including meansfor operating said second shift means when said image stored in saidsecond data storage means is inside said region of interest, and seconddisabling means for disabling said second shift means and operating saidfirst shift means when said image stored in said second data storagemeans is outside said region of interest.
 41. A system according toclaim 27, wherein said image acquisition means comprises a CCD array anda programmable imager CCD controller coupled to said CCD array.
 42. Asystem according to claim 27, wherein said image acquisition meanscomprises photo-sensitive means for acquiring said image in response toan acquisition signal containing selected image acquisition parameters,and programmable control means in circuit with said photo-sensitivemeans for generating said acquisition signal and for programmablyaltering during acquisition of said image said selected imageacquisition parameters.
 43. A system according to claim 42, wherein saidprogrammable control means comprises: a controller adapted to beprogrammed with said selected image acquisition parameters and forgenerating said acquisition signal in response to a loading signal, andparameter loading means coupled to said controller for generating saidloading signal and for receiving said image acquisition parameters. 44.A system according to claim 42, wherein said programmable control meansincludes a programmable imager controller circuit, said controllercircuit being adapted to be programmed with said image acquisitionparameters.
 45. A system according to claim 44, wherein saidprogrammable imager controller circuit includes means for receiving saidimage acquisition parameters in less than or equal to about 2 μs.
 46. Asystem according to claim 42, wherein said programmable imagercontroller circuit includes means for reprogramming said controllercircuit on the fly, in essentially real time.
 47. A system according toclaim 44, wherein said programmable imager controller circuit operatesat a driving frequency, said programmable imager controller circuitcomprising means for automatically changing said driving frequencyduring acquisition of said image.
 48. A system according to claim 43,further comprising triggering means for generating a trigger signal inresponse to an input command signal, said parameter loading meansgenerating said loading signal in response to said trigger signal, andparameter memory means coupled to said paramter loading means forreceiving and storing said image acquisition parameters from the hostprocessor.
 49. A system according to claim 27, wherein said imageacquisition means further includes triggering means for generating anoutput trigger signal in response to a command signal, parameter memorymeans adapted for receiving said image acquisition parameters from thehost processor, and a camera loader circuit adapted to receive saidselected image acquisition parameters from said parameter memory meansand said output trigger signal, for programming said programmablecontrol means with said image acquisition parameters.
 50. A systemaccording to claim 27, wherein said memory means comprises a data FIFOregister, wherein said means for transferring transfers said image intosaid register.
 51. A system according to claim 50, further comprisingdata transfer means for transferring said image data accumulated in saiddata FIFO register to the host computing system.
 52. A system accordingto claim 51, wherein said transfer of data from said data FIFO registeris a direct memory address transfer, thereby substantially reducing thenumber of times the system interrupts the host processor.
 53. A systemaccording to claim 27, further comprising pre-processing means separatefrom the host processor for receiving said image data and for at leastpartially processing said data without interrupting said host processor.54. A system according to claim 14, wherein said means for interruptingis coupled to said data FIFO register and to said image acquisitionmeans for interrupting said acquisition of said image when said dataFIFO register is full, thereby permitting reliable transfer of datacorresponding to said image.
 55. A system according to claim 51, whereinsaid data transfer means transfers data from said data FIFO registersubstantially independently of the memory manager of the host computingsystem.
 56. A system according to claim 27, wherein said means fortransferring is adapted for immediately and temporarily interruptingsaid acquisition of said image.
 57. A system according to claim 42,wherein the host processor allocates memory for storage of said image,and wherein said programmable control means generates said acquisitionsignal substantially independently of allocation of the memory by thehost processor.
 58. A system according to claim 42, wherein the hostprocessor allocates memory for storage of said image, and wherein saidprogrammable control means generates said acquisition signal in parallelwith and substantially independently of allocation of the memory by thehost processor.
 59. A system for transmitting an image to a machinevision system having a host processor that allocates memory for storageof said image, said system comprising: image acquisition means foracquiring at least a portion of said image in response to a triggersignal; image transfer means for transferring said image from said imageacquisition means to memory allocated by the host processor, said imagetransfer means including transfer interruption means for interruptingtransfer of said image to memory at an interruption point, buffer meanscoupled to receive data representative of an image from said imageacquisition means for storing said data during the operation of saidtransfer interruption means, and transfer resumption means to resumetransfer of said image to memory from said interruption point.
 60. Animage acquisition system for connection to a machine vision system foracquiring an image of an object, said systen having a host processor andcomprising: image acquisition means for acquiring said image of theobject, said image acquisition means including photo-sensitive means foracquiring said image in response to an acquisition signal containingselected image acquisition parameters, and programmable control means incircuit with said photo-sensitive means for generating said acquisitionsignal and for programmably altering during acquisition of said imagesaid selected image acquisition parameters, memory means for storing atleast a portion of said image, and transfer means for transferring saidimage from said image acquisition means to said memory means.
 61. Theimage acquisition system of claim 60, wherein said photo-sensitive meansincludes a CCD array and said programmable control means includes aprogrammable imager CCD controller.
 62. The image acquisition system ofclaim 60, wherein said programmable control means comprises: acontroller adapted to be programmed with said selected image acquisitionparameters and for generating said acquisition signal in response to aloading signal, and parameter loading means coupled to said controllerfor generating said actuation signal and for receiving said imageacquisition parameters.
 63. The image acquisition system of claim 60,wherein said programmable control means includes a programmable imagercontroller circuit, said controller circuit being adapted to beprogrammed with said image acquisition parameters.
 64. The imageacquisition system of claim 63, wherein said programmable imagercontroller circuit includes means for receiving said image acquisitionparameters in less than or equal to about 2 μs.
 65. The imageacquisition system of claim 63, wherein said programmable imagercontroller circuit includes means for reprogramming said circuit on thefly, in essentially real time.
 66. The image acquisition system of claim63, wherein said programmable imager controller circuit operates at adriving frequency, said programmable imager controller circuitcomprising means for automatically changing said driving frequencyduring acquisition of said image.
 67. The image acquisition system ofclaim 62, further comprising triggering means for generating a triggersignal in response to an input command signal, said parameter loadingmeans generating said loading signal in response to said trigger signal,and parameter memory means for receiving and storing said imageacquisition parameters from the host processor.
 68. The imageacquisition system of claim 60, wherein said image acquisition meansfurther includes triggering means for generating an output triggersignal in response to a command signal, parameter memory means adaptedfor receiving said image acquisition parameters from the host processor,and a camera loader circuit adapted to receive said selected imageacquisition parameters from said parameter memory means and said outputtrigger signal, for programming said programmable control means withsaid image acquisition parameters.
 69. The image acquisition system ofclaim 60, wherein said memory means comprises one or more verticalregisters coupled to said photo-sensitive means for storing opticalenergy representative of said acquired image, and one or more horizontalregisters positioned to receive at least a portion of said opticalenergy stored in said vertical register.
 70. The image acquisitionsystem of claim 69, wherein said photo-sensitive means is adapted toacquire a region of interest corresponding to at least a portion of saidimage, further comprising second means for transferring a portion ofsaid optical energy corresponding to a portion of said region ofinterest from said vertical register to said horizontal register, anddisabling means for disabling transfer of optical energy from saidhorizontal energy during said transfer of optical energy from saidvertical register into said horizontal register, whereby said opticalenergy corresponding to a portion of said region of interest is rapidlytransferred from said vertical register to said horizontal registerwithout actively removing said transferred energy from said horizontalregister.
 71. The image acquisition system of claim 70, wherein saidphoto-sensitive means is adapted to acquire a region of interestcorresponding to at least a portion of said image, further comprisingsecond means for transferring a portion of said energy stored in saidvertical register corresponding to a portion of said region of interestto said horizontal register, enabling means for enabling transfer ofoptical energy stored in said horizontal register therefrom, anddisabling means for disabling transfer of optical energy from saidvertical register into said horizontal register during said transfer ofoptical energy out of said horizontal register.
 72. The imageacquisition system of claim 60, wherein said memory means comprises adata FIFO register, wherein said transfer means transfers said imageinto said register.
 73. The image acquisition system of claim 72,further comprising second transfer means for transferring said imagedata accumulated in said data FIFO register to the host computingsystem.
 74. The image acquisition system of claim 72, further comprisingmemory address transfer means for transferring said data stored in saiddata FIFO register directly to an address in the host computing system,thereby substantially reducing the number of times the system interruptsthe host processor.
 75. The image acquisition system of claim 72,further comprising pre-processing means separate from the host processorfor receiving said image data and for at least partially processing saiddata without interrupting said host processor.
 76. The image acquisitionsystem of claim 72, further comprising interrupt means coupled to saiddata FIFO register and to said image acquisition means for interruptingsaid acquisition of said image when said data FIFO register is full,thereby permitting reliable transfer of data corresponding to saidimage.
 77. The image acquisition system of claim 76, wherein saidinterrupt means is capable of interrupting said acquisition of saidimage between lines corresponding to said image.
 78. The imageacquisition system of claim 15, wherein said second transfer meanstransfers data from said data FIFO register substantially independentlyof the memory manager of the host computing system.
 79. The imageacquisition system of claim 76, wherein said interrupt means is adaptedfor immediately and temporarily interrupting said acquisition of saidimage.
 80. The image acquisition system of claim 60, wherein the hostprocessor allocates memory for storage of said image, and wherein saidprogrammable control means generates said acquisition signalsubstantially independently of allocation of the memory by the hostprocessor.
 81. The image acquisition system of claim 60, wherein thehost processor allocates memory for storage of said image, and whereinsaid programmable control means generates said acquisition signal inparallel with and substantially independently of allocation of thememory by the host processor.
 82. The image acquisition system of claim60, wherein said image acquired by said image acquisition means includesa plurality of pixels, further comprising pixel correction means incircuit with said image acquisition means for correcting said pixelsprior to transfer to said memory means.
 83. The image acquisition systemof claim 82, wherein said pixel correction means comprises second memorymeans for storing a plurality of pre-determined pixel correction valuescorresponding to each pixel of said image, and multiplier means formultiplying each pixel of said image by said corresponding pixelcorrection value, thereby forming a corrected pixel.
 84. The imageacquisition system of claim 82, wherein said pixel correction means isseparate from one of the host processor and the host computing systemand performs said pixel correction in real time.
 85. The imageacquisition system of claim 60, wherein a region of interestcorresponding to a portion of said image includes a selected number ofpixels, further comprising pixel evaluation memory means coupled toimage acquisition means for storing a value corresponding to said pixelsof said region of interest,and pre-determined pixel storage meanscoupled to said image acquisition means for storing a valuecorresponding to a predetermined number of pixels.
 86. The imageacquisition system of claim 85, further comprising comparing means forcomparing said value stored in said pixel evaluation means with saidvalue stored in said predetermined pixel storage means, and means forgenerating a match signal when said values are equal, said programmablecontrol means including means for receiving said match signal and foraltering said image acquisition parameters.